--------------------------------------------------------------------------------
--                     LeftShifter_8_by_max_16_F400_uid4
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved 
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2011)
--------------------------------------------------------------------------------
-- Pipeline depth: 1 cycles

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;

entity LeftShifter_8_by_max_16_F400_uid4 is
   port ( clk, rst, ce : in std_logic;
          X : in  std_logic_vector(7 downto 0);
          S : in  std_logic_vector(4 downto 0);
          R : out  std_logic_vector(23 downto 0)   );
end entity;

architecture arch of LeftShifter_8_by_max_16_F400_uid4 is
signal level0 :  std_logic_vector(7 downto 0);
signal ps, ps_d1 :  std_logic_vector(4 downto 0);
signal level1 :  std_logic_vector(8 downto 0);
signal level2 :  std_logic_vector(10 downto 0);
signal level3, level3_d1 :  std_logic_vector(14 downto 0);
signal level4 :  std_logic_vector(22 downto 0);
signal level5 :  std_logic_vector(38 downto 0);
begin
   process(clk)
      begin
         if clk'event and clk = '1' then
            if ce = '1' then
               ps_d1 <=  ps;
               level3_d1 <=  level3;
            end if;
         end if;
      end process;
   level0<= X;
   ps<= S;
   level1<= level0 & (0 downto 0 => '0') when ps(0)= '1' else     (0 downto 0 => '0') & level0;
   level2<= level1 & (1 downto 0 => '0') when ps(1)= '1' else     (1 downto 0 => '0') & level1;
   level3<= level2 & (3 downto 0 => '0') when ps(2)= '1' else     (3 downto 0 => '0') & level2;
   ----------------Synchro barrier, entering cycle 1----------------
   level4<= level3_d1 & (7 downto 0 => '0') when ps_d1(3)= '1' else     (7 downto 0 => '0') & level3_d1;
   level5<= level4 & (15 downto 0 => '0') when ps_d1(4)= '1' else     (15 downto 0 => '0') & level4;
   R <= level5(23 downto 0);
end architecture;

--------------------------------------------------------------------------------
--            FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_Table_0
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved 
-- Authors: Florent de Dinechin (2007-2011-?), 3IF Dev Team
--------------------------------------------------------------------------------
library ieee; 
use ieee.std_logic_1164.all;
library work;
entity FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_Table_0 is
   port ( clk, rst, ce : in std_logic;
          X : in  std_logic_vector(5 downto 0);
          Y : out  std_logic_vector(11 downto 0)   );
end entity;

architecture arch of FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_Table_0 is
signal TableOut :  std_logic_vector(11 downto 0);
begin
   process(clk)
      begin
         if clk'event and clk = '1' then
            if ce = '1' then
            end if;
         end if;
      end process;
  with X select TableOut <= 
   "000000001000" when "000000",
   "000000110110" when "000001",
   "000001100100" when "000010",
   "000010010010" when "000011",
   "000011000001" when "000100",
   "000011101111" when "000101",
   "000100011101" when "000110",
   "000101001011" when "000111",
   "000101111001" when "001000",
   "000110100111" when "001001",
   "000111010110" when "001010",
   "001000000100" when "001011",
   "001000110010" when "001100",
   "001001100000" when "001101",
   "001010001110" when "001110",
   "001010111100" when "001111",
   "001011101011" when "010000",
   "001100011001" when "010001",
   "001101000111" when "010010",
   "001101110101" when "010011",
   "001110100011" when "010100",
   "001111010001" when "010101",
   "010000000000" when "010110",
   "010000101110" when "010111",
   "010001011100" when "011000",
   "010010001010" when "011001",
   "010010111000" when "011010",
   "010011100110" when "011011",
   "010100010101" when "011100",
   "010101000011" when "011101",
   "010101110001" when "011110",
   "010110011111" when "011111",
   "010111001101" when "100000",
   "010111111011" when "100001",
   "011000101010" when "100010",
   "011001011000" when "100011",
   "011010000110" when "100100",
   "011010110100" when "100101",
   "011011100010" when "100110",
   "011100010000" when "100111",
   "011100111111" when "101000",
   "011101101101" when "101001",
   "011110011011" when "101010",
   "011111001001" when "101011",
   "011111110111" when "101100",
   "100000100101" when "101101",
   "100001010100" when "101110",
   "100010000010" when "101111",
   "100010110000" when "110000",
   "100011011110" when "110001",
   "100100001100" when "110010",
   "100100111010" when "110011",
   "100101101001" when "110100",
   "100110010111" when "110101",
   "100111000101" when "110110",
   "100111110011" when "110111",
   "101000100001" when "111000",
   "101001001111" when "111001",
   "101001111110" when "111010",
   "101010101100" when "111011",
   "101011011010" when "111100",
   "101100001000" when "111101",
   "101100110110" when "111110",
   "101101100100" when "111111",
   "------------" when others;
    Y <= TableOut;
end architecture;

--------------------------------------------------------------------------------
--            FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_Table_1
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved 
-- Authors: Florent de Dinechin (2007-2011-?), 3IF Dev Team
--------------------------------------------------------------------------------
library ieee; 
use ieee.std_logic_1164.all;
library work;
entity FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_Table_1 is
   port ( clk, rst, ce : in std_logic;
          X : in  std_logic_vector(3 downto 0);
          Y : out  std_logic_vector(5 downto 0)   );
end entity;

architecture arch of FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_Table_1 is
signal TableOut :  std_logic_vector(5 downto 0);
begin
   process(clk)
      begin
         if clk'event and clk = '1' then
            if ce = '1' then
            end if;
         end if;
      end process;
  with X select TableOut <= 
   "000000" when "0000",
   "000011" when "0001",
   "000110" when "0010",
   "001001" when "0011",
   "001100" when "0100",
   "001110" when "0101",
   "010001" when "0110",
   "010100" when "0111",
   "010111" when "1000",
   "011010" when "1001",
   "011101" when "1010",
   "100000" when "1011",
   "100011" when "1100",
   "100110" when "1101",
   "101000" when "1110",
   "101011" when "1111",
   "------" when others;
    Y <= TableOut;
end architecture;

--------------------------------------------------------------------------------
--                           IntAdder_13_f400_uid24
--                     (IntAdderClassical_13_F400_uid26)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved 
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2010)
--------------------------------------------------------------------------------
-- Pipeline depth: 0 cycles

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;

entity IntAdder_13_f400_uid24 is
   port ( clk, rst, ce : in std_logic;
          X : in  std_logic_vector(12 downto 0);
          Y : in  std_logic_vector(12 downto 0);
          Cin : in  std_logic;
          R : out  std_logic_vector(12 downto 0)   );
end entity;

architecture arch of IntAdder_13_f400_uid24 is
begin
   process(clk)
      begin
         if clk'event and clk = '1' then
            if ce = '1' then
            end if;
         end if;
      end process;
   --Classical
    R <= X + Y + Cin;
end architecture;

--------------------------------------------------------------------------------
--                FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved 
-- Authors: Florent de Dinechin (2007-2016)
--------------------------------------------------------------------------------
-- Pipeline depth: 0 cycles

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;

entity FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8 is
   port ( clk, rst, ce : in std_logic;
          X : in  std_logic_vector(9 downto 0);
          R : out  std_logic_vector(7 downto 0)   );
end entity;

architecture arch of FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8 is
   component FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_Table_0 is
      port ( clk, rst, ce : in std_logic;
             X : in  std_logic_vector(5 downto 0);
             Y : out  std_logic_vector(11 downto 0)   );
   end component;

   component FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_Table_1 is
      port ( clk, rst, ce : in std_logic;
             X : in  std_logic_vector(3 downto 0);
             Y : out  std_logic_vector(5 downto 0)   );
   end component;

   component IntAdder_13_f400_uid24 is
      port ( clk, rst, ce : in std_logic;
             X : in  std_logic_vector(12 downto 0);
             Y : in  std_logic_vector(12 downto 0);
             Cin : in  std_logic;
             R : out  std_logic_vector(12 downto 0)   );
   end component;

signal FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_A0 :  std_logic_vector(5 downto 0);
signal FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T0 :  std_logic_vector(11 downto 0);
signal heap_bh9_w0_0 :  std_logic;
signal heap_bh9_w1_0 :  std_logic;
signal heap_bh9_w2_0 :  std_logic;
signal heap_bh9_w3_0 :  std_logic;
signal heap_bh9_w4_0 :  std_logic;
signal heap_bh9_w5_0 :  std_logic;
signal heap_bh9_w6_0 :  std_logic;
signal heap_bh9_w7_0 :  std_logic;
signal heap_bh9_w8_0 :  std_logic;
signal heap_bh9_w9_0 :  std_logic;
signal heap_bh9_w10_0 :  std_logic;
signal heap_bh9_w11_0 :  std_logic;
signal FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_A1 :  std_logic_vector(3 downto 0);
signal FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T1 :  std_logic_vector(5 downto 0);
signal heap_bh9_w0_1 :  std_logic;
signal heap_bh9_w1_1 :  std_logic;
signal heap_bh9_w2_1 :  std_logic;
signal heap_bh9_w3_1 :  std_logic;
signal heap_bh9_w4_1 :  std_logic;
signal heap_bh9_w5_1 :  std_logic;
signal finalAdderIn0_bh9 :  std_logic_vector(12 downto 0);
signal finalAdderIn1_bh9 :  std_logic_vector(12 downto 0);
signal finalAdderCin_bh9 :  std_logic;
signal finalAdderOut_bh9 :  std_logic_vector(12 downto 0);
signal CompressionResult9 :  std_logic_vector(12 downto 0);
signal OutRes :  std_logic_vector(11 downto 0);
begin
   process(clk)
      begin
         if clk'event and clk = '1' then
            if ce = '1' then
            end if;
         end if;
      end process;
   FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_A0 <= X(9 downto 4); -- input address  m=6  l=1
   FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_Table0: FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_Table_0  -- pipelineDepth=0 maxInDelay=0
      port map ( clk  => clk,
                 rst  => rst,
                 ce => ce,
                 X => FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_A0,
                 Y => FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T0);
   ---------------- cycle 0----------------
   heap_bh9_w0_0 <= FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T0(0); -- cycle= 0 cp= 0
   heap_bh9_w1_0 <= FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T0(1); -- cycle= 0 cp= 0
   heap_bh9_w2_0 <= FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T0(2); -- cycle= 0 cp= 0
   heap_bh9_w3_0 <= FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T0(3); -- cycle= 0 cp= 0
   heap_bh9_w4_0 <= FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T0(4); -- cycle= 0 cp= 0
   heap_bh9_w5_0 <= FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T0(5); -- cycle= 0 cp= 0
   heap_bh9_w6_0 <= FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T0(6); -- cycle= 0 cp= 0
   heap_bh9_w7_0 <= FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T0(7); -- cycle= 0 cp= 0
   heap_bh9_w8_0 <= FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T0(8); -- cycle= 0 cp= 0
   heap_bh9_w9_0 <= FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T0(9); -- cycle= 0 cp= 0
   heap_bh9_w10_0 <= FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T0(10); -- cycle= 0 cp= 0
   heap_bh9_w11_0 <= FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T0(11); -- cycle= 0 cp= 0
   FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_A1 <= X(3 downto 0); -- input address  m=0  l=-3
   FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_Table1: FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_Table_1  -- pipelineDepth=0 maxInDelay=0
      port map ( clk  => clk,
                 rst  => rst,
                 ce => ce,
                 X => FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_A1,
                 Y => FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T1);
   ---------------- cycle 0----------------
   heap_bh9_w0_1 <= FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T1(0); -- cycle= 0 cp= 0
   heap_bh9_w1_1 <= FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T1(1); -- cycle= 0 cp= 0
   heap_bh9_w2_1 <= FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T1(2); -- cycle= 0 cp= 0
   heap_bh9_w3_1 <= FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T1(3); -- cycle= 0 cp= 0
   heap_bh9_w4_1 <= FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T1(4); -- cycle= 0 cp= 0
   heap_bh9_w5_1 <= FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8_T1(5); -- cycle= 0 cp= 0
   
   -- Beginning of code generated by BitHeap::generateCompressorVHDL
   -- code generated by BitHeap::generateSupertileVHDL()
   ----------------Synchro barrier, entering cycle 0----------------

   -- Adding the constant bits
      -- All the constant bits are zero, nothing to add

   ----------------Synchro barrier, entering cycle 0----------------
   ----------------Synchro barrier, entering cycle 0----------------
   finalAdderIn0_bh9 <= "0" & heap_bh9_w11_0 & heap_bh9_w10_0 & heap_bh9_w9_0 & heap_bh9_w8_0 & heap_bh9_w7_0 & heap_bh9_w6_0 & heap_bh9_w5_1 & heap_bh9_w4_1 & heap_bh9_w3_1 & heap_bh9_w2_1 & heap_bh9_w1_1 & heap_bh9_w0_1;
   finalAdderIn1_bh9 <= "0" & '0' & '0' & '0' & '0' & '0' & '0' & heap_bh9_w5_0 & heap_bh9_w4_0 & heap_bh9_w3_0 & heap_bh9_w2_0 & heap_bh9_w1_0 & heap_bh9_w0_0;
   finalAdderCin_bh9 <= '0';
      Adder_final9_0: IntAdder_13_f400_uid24  -- pipelineDepth=0 maxInDelay=0
      port map ( clk  => clk,
                 rst  => rst,
                 ce => ce,
                 Cin => finalAdderCin_bh9,
                 R => finalAdderOut_bh9,
                 X => finalAdderIn0_bh9,
                 Y => finalAdderIn1_bh9);
   -- concatenate all the compressed chunks
   CompressionResult9 <= finalAdderOut_bh9;
   -- End of code generated by BitHeap::generateCompressorVHDL
OutRes <= CompressionResult9(11 downto 0);
   R <= OutRes(11 downto 4);
end architecture;

--------------------------------------------------------------------------------
--            FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_Table_0
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved 
-- Authors: Florent de Dinechin (2007-2011-?), 3IF Dev Team
--------------------------------------------------------------------------------
library ieee; 
use ieee.std_logic_1164.all;
library work;
entity FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_Table_0 is
   port ( clk, rst, ce : in std_logic;
          X : in  std_logic_vector(5 downto 0);
          Y : out  std_logic_vector(16 downto 0)   );
end entity;

architecture arch of FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_Table_0 is
signal TableOut :  std_logic_vector(16 downto 0);
begin
   process(clk)
      begin
         if clk'event and clk = '1' then
            if ce = '1' then
            end if;
         end if;
      end process;
  with X select TableOut <= 
   "00000000000000000" when "000000",
   "00000010110001100" when "000001",
   "00000101100010111" when "000010",
   "00001000010100011" when "000011",
   "00001011000101110" when "000100",
   "00001101110111010" when "000101",
   "00010000101000101" when "000110",
   "00010011011010001" when "000111",
   "00010110001011101" when "001000",
   "00011000111101000" when "001001",
   "00011011101110100" when "001010",
   "00011110011111111" when "001011",
   "00100001010001011" when "001100",
   "00100100000010110" when "001101",
   "00100110110100010" when "001110",
   "00101001100101101" when "001111",
   "00101100010111001" when "010000",
   "00101111001000101" when "010001",
   "00110001111010000" when "010010",
   "00110100101011100" when "010011",
   "00110111011100111" when "010100",
   "00111010001110011" when "010101",
   "00111100111111110" when "010110",
   "00111111110001010" when "010111",
   "01000010100010110" when "011000",
   "01000101010100001" when "011001",
   "01001000000101101" when "011010",
   "01001010110111000" when "011011",
   "01001101101000100" when "011100",
   "01010000011001111" when "011101",
   "01010011001011011" when "011110",
   "01010101111100111" when "011111",
   "01011000101110010" when "100000",
   "01011011011111110" when "100001",
   "01011110010001001" when "100010",
   "01100001000010101" when "100011",
   "01100011110100000" when "100100",
   "01100110100101100" when "100101",
   "01101001010110111" when "100110",
   "01101100001000011" when "100111",
   "01101110111001111" when "101000",
   "01110001101011010" when "101001",
   "01110100011100110" when "101010",
   "01110111001110001" when "101011",
   "01111001111111101" when "101100",
   "01111100110001000" when "101101",
   "01111111100010100" when "101110",
   "10000010010100000" when "101111",
   "10000101000101011" when "110000",
   "10000111110110111" when "110001",
   "10001010101000010" when "110010",
   "10001101011001110" when "110011",
   "10010000001011001" when "110100",
   "10010010111100101" when "110101",
   "10010101101110001" when "110110",
   "10011000011111100" when "110111",
   "10011011010001000" when "111000",
   "10011110000010011" when "111001",
   "10100000110011111" when "111010",
   "10100011100101010" when "111011",
   "10100110010110110" when "111100",
   "10101001001000001" when "111101",
   "10101011111001101" when "111110",
   "10101110101011001" when "111111",
   "-----------------" when others;
    Y <= TableOut;
end architecture;

--------------------------------------------------------------------------------
--            FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_Table_1
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved 
-- Authors: Florent de Dinechin (2007-2011-?), 3IF Dev Team
--------------------------------------------------------------------------------
library ieee; 
use ieee.std_logic_1164.all;
library work;
entity FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_Table_1 is
   port ( clk, rst, ce : in std_logic;
          X : in  std_logic_vector(1 downto 0);
          Y : out  std_logic_vector(10 downto 0)   );
end entity;

architecture arch of FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_Table_1 is
signal TableOut :  std_logic_vector(10 downto 0);
begin
   process(clk)
      begin
         if clk'event and clk = '1' then
            if ce = '1' then
            end if;
         end if;
      end process;
  with X select TableOut <= 
   "00000000000" when "00",
   "00101100011" when "01",
   "01011000110" when "10",
   "10000101001" when "11",
   "-----------" when others;
    Y <= TableOut;
end architecture;

--------------------------------------------------------------------------------
--                           IntAdder_18_f400_uid50
--                     (IntAdderClassical_18_F400_uid52)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved 
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2010)
--------------------------------------------------------------------------------
-- Pipeline depth: 0 cycles

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;

entity IntAdder_18_f400_uid50 is
   port ( clk, rst, ce : in std_logic;
          X : in  std_logic_vector(17 downto 0);
          Y : in  std_logic_vector(17 downto 0);
          Cin : in  std_logic;
          R : out  std_logic_vector(17 downto 0)   );
end entity;

architecture arch of IntAdder_18_f400_uid50 is
begin
   process(clk)
      begin
         if clk'event and clk = '1' then
            if ce = '1' then
            end if;
         end if;
      end process;
   --Classical
    R <= X + Y + Cin;
end architecture;

--------------------------------------------------------------------------------
--                FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved 
-- Authors: Florent de Dinechin (2007-2016)
--------------------------------------------------------------------------------
-- Pipeline depth: 0 cycles

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;

entity FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34 is
   port ( clk, rst, ce : in std_logic;
          X : in  std_logic_vector(7 downto 0);
          R : out  std_logic_vector(16 downto 0)   );
end entity;

architecture arch of FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34 is
   component FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_Table_0 is
      port ( clk, rst, ce : in std_logic;
             X : in  std_logic_vector(5 downto 0);
             Y : out  std_logic_vector(16 downto 0)   );
   end component;

   component FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_Table_1 is
      port ( clk, rst, ce : in std_logic;
             X : in  std_logic_vector(1 downto 0);
             Y : out  std_logic_vector(10 downto 0)   );
   end component;

   component IntAdder_18_f400_uid50 is
      port ( clk, rst, ce : in std_logic;
             X : in  std_logic_vector(17 downto 0);
             Y : in  std_logic_vector(17 downto 0);
             Cin : in  std_logic;
             R : out  std_logic_vector(17 downto 0)   );
   end component;

signal FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_A0 :  std_logic_vector(5 downto 0);
signal FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T0 :  std_logic_vector(16 downto 0);
signal heap_bh35_w0_0 :  std_logic;
signal heap_bh35_w1_0 :  std_logic;
signal heap_bh35_w2_0 :  std_logic;
signal heap_bh35_w3_0 :  std_logic;
signal heap_bh35_w4_0 :  std_logic;
signal heap_bh35_w5_0 :  std_logic;
signal heap_bh35_w6_0 :  std_logic;
signal heap_bh35_w7_0 :  std_logic;
signal heap_bh35_w8_0 :  std_logic;
signal heap_bh35_w9_0 :  std_logic;
signal heap_bh35_w10_0 :  std_logic;
signal heap_bh35_w11_0 :  std_logic;
signal heap_bh35_w12_0 :  std_logic;
signal heap_bh35_w13_0 :  std_logic;
signal heap_bh35_w14_0 :  std_logic;
signal heap_bh35_w15_0 :  std_logic;
signal heap_bh35_w16_0 :  std_logic;
signal FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_A1 :  std_logic_vector(1 downto 0);
signal FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T1 :  std_logic_vector(10 downto 0);
signal heap_bh35_w0_1 :  std_logic;
signal heap_bh35_w1_1 :  std_logic;
signal heap_bh35_w2_1 :  std_logic;
signal heap_bh35_w3_1 :  std_logic;
signal heap_bh35_w4_1 :  std_logic;
signal heap_bh35_w5_1 :  std_logic;
signal heap_bh35_w6_1 :  std_logic;
signal heap_bh35_w7_1 :  std_logic;
signal heap_bh35_w8_1 :  std_logic;
signal heap_bh35_w9_1 :  std_logic;
signal heap_bh35_w10_1 :  std_logic;
signal finalAdderIn0_bh35 :  std_logic_vector(17 downto 0);
signal finalAdderIn1_bh35 :  std_logic_vector(17 downto 0);
signal finalAdderCin_bh35 :  std_logic;
signal finalAdderOut_bh35 :  std_logic_vector(17 downto 0);
signal CompressionResult35 :  std_logic_vector(17 downto 0);
signal OutRes :  std_logic_vector(16 downto 0);
begin
   process(clk)
      begin
         if clk'event and clk = '1' then
            if ce = '1' then
            end if;
         end if;
      end process;
   FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_A0 <= X(7 downto 2); -- input address  m=7  l=2
   FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_Table0: FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_Table_0  -- pipelineDepth=0 maxInDelay=0
      port map ( clk  => clk,
                 rst  => rst,
                 ce => ce,
                 X => FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_A0,
                 Y => FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T0);
   ---------------- cycle 0----------------
   heap_bh35_w0_0 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T0(0); -- cycle= 0 cp= 0
   heap_bh35_w1_0 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T0(1); -- cycle= 0 cp= 0
   heap_bh35_w2_0 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T0(2); -- cycle= 0 cp= 0
   heap_bh35_w3_0 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T0(3); -- cycle= 0 cp= 0
   heap_bh35_w4_0 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T0(4); -- cycle= 0 cp= 0
   heap_bh35_w5_0 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T0(5); -- cycle= 0 cp= 0
   heap_bh35_w6_0 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T0(6); -- cycle= 0 cp= 0
   heap_bh35_w7_0 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T0(7); -- cycle= 0 cp= 0
   heap_bh35_w8_0 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T0(8); -- cycle= 0 cp= 0
   heap_bh35_w9_0 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T0(9); -- cycle= 0 cp= 0
   heap_bh35_w10_0 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T0(10); -- cycle= 0 cp= 0
   heap_bh35_w11_0 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T0(11); -- cycle= 0 cp= 0
   heap_bh35_w12_0 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T0(12); -- cycle= 0 cp= 0
   heap_bh35_w13_0 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T0(13); -- cycle= 0 cp= 0
   heap_bh35_w14_0 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T0(14); -- cycle= 0 cp= 0
   heap_bh35_w15_0 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T0(15); -- cycle= 0 cp= 0
   heap_bh35_w16_0 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T0(16); -- cycle= 0 cp= 0
   FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_A1 <= X(1 downto 0); -- input address  m=1  l=0
   FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_Table1: FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_Table_1  -- pipelineDepth=0 maxInDelay=0
      port map ( clk  => clk,
                 rst  => rst,
                 ce => ce,
                 X => FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_A1,
                 Y => FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T1);
   ---------------- cycle 0----------------
   heap_bh35_w0_1 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T1(0); -- cycle= 0 cp= 0
   heap_bh35_w1_1 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T1(1); -- cycle= 0 cp= 0
   heap_bh35_w2_1 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T1(2); -- cycle= 0 cp= 0
   heap_bh35_w3_1 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T1(3); -- cycle= 0 cp= 0
   heap_bh35_w4_1 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T1(4); -- cycle= 0 cp= 0
   heap_bh35_w5_1 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T1(5); -- cycle= 0 cp= 0
   heap_bh35_w6_1 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T1(6); -- cycle= 0 cp= 0
   heap_bh35_w7_1 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T1(7); -- cycle= 0 cp= 0
   heap_bh35_w8_1 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T1(8); -- cycle= 0 cp= 0
   heap_bh35_w9_1 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T1(9); -- cycle= 0 cp= 0
   heap_bh35_w10_1 <= FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34_T1(10); -- cycle= 0 cp= 0
   
   -- Beginning of code generated by BitHeap::generateCompressorVHDL
   -- code generated by BitHeap::generateSupertileVHDL()
   ----------------Synchro barrier, entering cycle 0----------------

   -- Adding the constant bits
      -- All the constant bits are zero, nothing to add

   ----------------Synchro barrier, entering cycle 0----------------
   ----------------Synchro barrier, entering cycle 0----------------
   finalAdderIn0_bh35 <= "0" & heap_bh35_w16_0 & heap_bh35_w15_0 & heap_bh35_w14_0 & heap_bh35_w13_0 & heap_bh35_w12_0 & heap_bh35_w11_0 & heap_bh35_w10_1 & heap_bh35_w9_1 & heap_bh35_w8_1 & heap_bh35_w7_1 & heap_bh35_w6_1 & heap_bh35_w5_1 & heap_bh35_w4_1 & heap_bh35_w3_1 & heap_bh35_w2_1 & heap_bh35_w1_1 & heap_bh35_w0_1;
   finalAdderIn1_bh35 <= "0" & '0' & '0' & '0' & '0' & '0' & '0' & heap_bh35_w10_0 & heap_bh35_w9_0 & heap_bh35_w8_0 & heap_bh35_w7_0 & heap_bh35_w6_0 & heap_bh35_w5_0 & heap_bh35_w4_0 & heap_bh35_w3_0 & heap_bh35_w2_0 & heap_bh35_w1_0 & heap_bh35_w0_0;
   finalAdderCin_bh35 <= '0';
      Adder_final35_0: IntAdder_18_f400_uid50  -- pipelineDepth=0 maxInDelay=0
      port map ( clk  => clk,
                 rst  => rst,
                 ce => ce,
                 Cin => finalAdderCin_bh35,
                 R => finalAdderOut_bh35,
                 X => finalAdderIn0_bh35,
                 Y => finalAdderIn1_bh35);
   -- concatenate all the compressed chunks
   CompressionResult35 <= finalAdderOut_bh35;
   -- End of code generated by BitHeap::generateCompressorVHDL
OutRes <= CompressionResult35(16 downto 0);
   R <= OutRes(16 downto 0);
end architecture;

--------------------------------------------------------------------------------
--                           IntAdder_9_f484_uid60
--                      (IntAdderClassical_9_F484_uid62)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved 
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2010)
--------------------------------------------------------------------------------
-- Pipeline depth: 0 cycles

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;

entity IntAdder_9_f484_uid60 is
   port ( clk, rst, ce : in std_logic;
          X : in  std_logic_vector(8 downto 0);
          Y : in  std_logic_vector(8 downto 0);
          Cin : in  std_logic;
          R : out  std_logic_vector(8 downto 0)   );
end entity;

architecture arch of IntAdder_9_f484_uid60 is
begin
   process(clk)
      begin
         if clk'event and clk = '1' then
            if ce = '1' then
            end if;
         end if;
      end process;
   --Classical
    R <= X + Y + Cin;
end architecture;

--------------------------------------------------------------------------------
--                         ExpYTable_9_12_F400_uid68
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved 
-- Authors: Florent de Dinechin (2007-2012)
--------------------------------------------------------------------------------
library ieee; 
use ieee.std_logic_1164.all;
library work;
entity ExpYTable_9_12_F400_uid68 is
   port ( clk, rst, ce : in std_logic;
          X : in  std_logic_vector(8 downto 0);
          Y : out  std_logic_vector(11 downto 0)   );
end entity;

architecture arch of ExpYTable_9_12_F400_uid68 is
signal TableOut :  std_logic_vector(11 downto 0);
begin
   process(clk)
      begin
         if clk'event and clk = '1' then
            if ce = '1' then
            end if;
         end if;
      end process;
  with X select TableOut <= 
   "100000000000" when "000000000",
   "100000000100" when "000000001",
   "100000001000" when "000000010",
   "100000001100" when "000000011",
   "100000010000" when "000000100",
   "100000010100" when "000000101",
   "100000011000" when "000000110",
   "100000011100" when "000000111",
   "100000100000" when "000001000",
   "100000100100" when "000001001",
   "100000101000" when "000001010",
   "100000101100" when "000001011",
   "100000110001" when "000001100",
   "100000110101" when "000001101",
   "100000111001" when "000001110",
   "100000111101" when "000001111",
   "100001000001" when "000010000",
   "100001000101" when "000010001",
   "100001001001" when "000010010",
   "100001001101" when "000010011",
   "100001010010" when "000010100",
   "100001010110" when "000010101",
   "100001011010" when "000010110",
   "100001011110" when "000010111",
   "100001100010" when "000011000",
   "100001100110" when "000011001",
   "100001101011" when "000011010",
   "100001101111" when "000011011",
   "100001110011" when "000011100",
   "100001110111" when "000011101",
   "100001111100" when "000011110",
   "100010000000" when "000011111",
   "100010000100" when "000100000",
   "100010001000" when "000100001",
   "100010001101" when "000100010",
   "100010010001" when "000100011",
   "100010010101" when "000100100",
   "100010011001" when "000100101",
   "100010011110" when "000100110",
   "100010100010" when "000100111",
   "100010100110" when "000101000",
   "100010101011" when "000101001",
   "100010101111" when "000101010",
   "100010110011" when "000101011",
   "100010111000" when "000101100",
   "100010111100" when "000101101",
   "100011000001" when "000101110",
   "100011000101" when "000101111",
   "100011001001" when "000110000",
   "100011001110" when "000110001",
   "100011010010" when "000110010",
   "100011010111" when "000110011",
   "100011011011" when "000110100",
   "100011011111" when "000110101",
   "100011100100" when "000110110",
   "100011101000" when "000110111",
   "100011101101" when "000111000",
   "100011110001" when "000111001",
   "100011110110" when "000111010",
   "100011111010" when "000111011",
   "100011111111" when "000111100",
   "100100000011" when "000111101",
   "100100001000" when "000111110",
   "100100001100" when "000111111",
   "100100010001" when "001000000",
   "100100010101" when "001000001",
   "100100011010" when "001000010",
   "100100011110" when "001000011",
   "100100100011" when "001000100",
   "100100100111" when "001000101",
   "100100101100" when "001000110",
   "100100110001" when "001000111",
   "100100110101" when "001001000",
   "100100111010" when "001001001",
   "100100111110" when "001001010",
   "100101000011" when "001001011",
   "100101001000" when "001001100",
   "100101001100" when "001001101",
   "100101010001" when "001001110",
   "100101010110" when "001001111",
   "100101011010" when "001010000",
   "100101011111" when "001010001",
   "100101100100" when "001010010",
   "100101101000" when "001010011",
   "100101101101" when "001010100",
   "100101110010" when "001010101",
   "100101110111" when "001010110",
   "100101111011" when "001010111",
   "100110000000" when "001011000",
   "100110000101" when "001011001",
   "100110001010" when "001011010",
   "100110001110" when "001011011",
   "100110010011" when "001011100",
   "100110011000" when "001011101",
   "100110011101" when "001011110",
   "100110100010" when "001011111",
   "100110100110" when "001100000",
   "100110101011" when "001100001",
   "100110110000" when "001100010",
   "100110110101" when "001100011",
   "100110111010" when "001100100",
   "100110111111" when "001100101",
   "100111000011" when "001100110",
   "100111001000" when "001100111",
   "100111001101" when "001101000",
   "100111010010" when "001101001",
   "100111010111" when "001101010",
   "100111011100" when "001101011",
   "100111100001" when "001101100",
   "100111100110" when "001101101",
   "100111101011" when "001101110",
   "100111110000" when "001101111",
   "100111110101" when "001110000",
   "100111111010" when "001110001",
   "100111111111" when "001110010",
   "101000000100" when "001110011",
   "101000001001" when "001110100",
   "101000001110" when "001110101",
   "101000010011" when "001110110",
   "101000011000" when "001110111",
   "101000011101" when "001111000",
   "101000100010" when "001111001",
   "101000100111" when "001111010",
   "101000101100" when "001111011",
   "101000110001" when "001111100",
   "101000110110" when "001111101",
   "101000111011" when "001111110",
   "101001000001" when "001111111",
   "101001000110" when "010000000",
   "101001001011" when "010000001",
   "101001010000" when "010000010",
   "101001010101" when "010000011",
   "101001011010" when "010000100",
   "101001011111" when "010000101",
   "101001100101" when "010000110",
   "101001101010" when "010000111",
   "101001101111" when "010001000",
   "101001110100" when "010001001",
   "101001111010" when "010001010",
   "101001111111" when "010001011",
   "101010000100" when "010001100",
   "101010001001" when "010001101",
   "101010001111" when "010001110",
   "101010010100" when "010001111",
   "101010011001" when "010010000",
   "101010011110" when "010010001",
   "101010100100" when "010010010",
   "101010101001" when "010010011",
   "101010101110" when "010010100",
   "101010110100" when "010010101",
   "101010111001" when "010010110",
   "101010111111" when "010010111",
   "101011000100" when "010011000",
   "101011001001" when "010011001",
   "101011001111" when "010011010",
   "101011010100" when "010011011",
   "101011011001" when "010011100",
   "101011011111" when "010011101",
   "101011100100" when "010011110",
   "101011101010" when "010011111",
   "101011101111" when "010100000",
   "101011110101" when "010100001",
   "101011111010" when "010100010",
   "101100000000" when "010100011",
   "101100000101" when "010100100",
   "101100001011" when "010100101",
   "101100010000" when "010100110",
   "101100010110" when "010100111",
   "101100011011" when "010101000",
   "101100100001" when "010101001",
   "101100100110" when "010101010",
   "101100101100" when "010101011",
   "101100110010" when "010101100",
   "101100110111" when "010101101",
   "101100111101" when "010101110",
   "101101000011" when "010101111",
   "101101001000" when "010110000",
   "101101001110" when "010110001",
   "101101010011" when "010110010",
   "101101011001" when "010110011",
   "101101011111" when "010110100",
   "101101100100" when "010110101",
   "101101101010" when "010110110",
   "101101110000" when "010110111",
   "101101110110" when "010111000",
   "101101111011" when "010111001",
   "101110000001" when "010111010",
   "101110000111" when "010111011",
   "101110001101" when "010111100",
   "101110010010" when "010111101",
   "101110011000" when "010111110",
   "101110011110" when "010111111",
   "101110100100" when "011000000",
   "101110101010" when "011000001",
   "101110101111" when "011000010",
   "101110110101" when "011000011",
   "101110111011" when "011000100",
   "101111000001" when "011000101",
   "101111000111" when "011000110",
   "101111001101" when "011000111",
   "101111010011" when "011001000",
   "101111011001" when "011001001",
   "101111011111" when "011001010",
   "101111100101" when "011001011",
   "101111101010" when "011001100",
   "101111110000" when "011001101",
   "101111110110" when "011001110",
   "101111111100" when "011001111",
   "110000000010" when "011010000",
   "110000001000" when "011010001",
   "110000001110" when "011010010",
   "110000010100" when "011010011",
   "110000011011" when "011010100",
   "110000100001" when "011010101",
   "110000100111" when "011010110",
   "110000101101" when "011010111",
   "110000110011" when "011011000",
   "110000111001" when "011011001",
   "110000111111" when "011011010",
   "110001000101" when "011011011",
   "110001001011" when "011011100",
   "110001010001" when "011011101",
   "110001011000" when "011011110",
   "110001011110" when "011011111",
   "110001100100" when "011100000",
   "110001101010" when "011100001",
   "110001110000" when "011100010",
   "110001110111" when "011100011",
   "110001111101" when "011100100",
   "110010000011" when "011100101",
   "110010001001" when "011100110",
   "110010010000" when "011100111",
   "110010010110" when "011101000",
   "110010011100" when "011101001",
   "110010100011" when "011101010",
   "110010101001" when "011101011",
   "110010101111" when "011101100",
   "110010110110" when "011101101",
   "110010111100" when "011101110",
   "110011000010" when "011101111",
   "110011001001" when "011110000",
   "110011001111" when "011110001",
   "110011010110" when "011110010",
   "110011011100" when "011110011",
   "110011100010" when "011110100",
   "110011101001" when "011110101",
   "110011101111" when "011110110",
   "110011110110" when "011110111",
   "110011111100" when "011111000",
   "110100000011" when "011111001",
   "110100001001" when "011111010",
   "110100010000" when "011111011",
   "110100010110" when "011111100",
   "110100011101" when "011111101",
   "110100100011" when "011111110",
   "110100101010" when "011111111",
   "010011011010" when "100000000",
   "010011011101" when "100000001",
   "010011011111" when "100000010",
   "010011100001" when "100000011",
   "010011100100" when "100000100",
   "010011100110" when "100000101",
   "010011101001" when "100000110",
   "010011101011" when "100000111",
   "010011101110" when "100001000",
   "010011110000" when "100001001",
   "010011110011" when "100001010",
   "010011110101" when "100001011",
   "010011111000" when "100001100",
   "010011111010" when "100001101",
   "010011111101" when "100001110",
   "010011111111" when "100001111",
   "010100000010" when "100010000",
   "010100000100" when "100010001",
   "010100000111" when "100010010",
   "010100001001" when "100010011",
   "010100001100" when "100010100",
   "010100001110" when "100010101",
   "010100010001" when "100010110",
   "010100010011" when "100010111",
   "010100010110" when "100011000",
   "010100011000" when "100011001",
   "010100011011" when "100011010",
   "010100011101" when "100011011",
   "010100100000" when "100011100",
   "010100100011" when "100011101",
   "010100100101" when "100011110",
   "010100101000" when "100011111",
   "010100101010" when "100100000",
   "010100101101" when "100100001",
   "010100101111" when "100100010",
   "010100110010" when "100100011",
   "010100110101" when "100100100",
   "010100110111" when "100100101",
   "010100111010" when "100100110",
   "010100111100" when "100100111",
   "010100111111" when "100101000",
   "010101000010" when "100101001",
   "010101000100" when "100101010",
   "010101000111" when "100101011",
   "010101001010" when "100101100",
   "010101001100" when "100101101",
   "010101001111" when "100101110",
   "010101010010" when "100101111",
   "010101010100" when "100110000",
   "010101010111" when "100110001",
   "010101011010" when "100110010",
   "010101011100" when "100110011",
   "010101011111" when "100110100",
   "010101100010" when "100110101",
   "010101100100" when "100110110",
   "010101100111" when "100110111",
   "010101101010" when "100111000",
   "010101101100" when "100111001",
   "010101101111" when "100111010",
   "010101110010" when "100111011",
   "010101110101" when "100111100",
   "010101110111" when "100111101",
   "010101111010" when "100111110",
   "010101111101" when "100111111",
   "010110000000" when "101000000",
   "010110000010" when "101000001",
   "010110000101" when "101000010",
   "010110001000" when "101000011",
   "010110001011" when "101000100",
   "010110001101" when "101000101",
   "010110010000" when "101000110",
   "010110010011" when "101000111",
   "010110010110" when "101001000",
   "010110011001" when "101001001",
   "010110011011" when "101001010",
   "010110011110" when "101001011",
   "010110100001" when "101001100",
   "010110100100" when "101001101",
   "010110100111" when "101001110",
   "010110101001" when "101001111",
   "010110101100" when "101010000",
   "010110101111" when "101010001",
   "010110110010" when "101010010",
   "010110110101" when "101010011",
   "010110111000" when "101010100",
   "010110111011" when "101010101",
   "010110111101" when "101010110",
   "010111000000" when "101010111",
   "010111000011" when "101011000",
   "010111000110" when "101011001",
   "010111001001" when "101011010",
   "010111001100" when "101011011",
   "010111001111" when "101011100",
   "010111010010" when "101011101",
   "010111010101" when "101011110",
   "010111010111" when "101011111",
   "010111011010" when "101100000",
   "010111011101" when "101100001",
   "010111100000" when "101100010",
   "010111100011" when "101100011",
   "010111100110" when "101100100",
   "010111101001" when "101100101",
   "010111101100" when "101100110",
   "010111101111" when "101100111",
   "010111110010" when "101101000",
   "010111110101" when "101101001",
   "010111111000" when "101101010",
   "010111111011" when "101101011",
   "010111111110" when "101101100",
   "011000000001" when "101101101",
   "011000000100" when "101101110",
   "011000000111" when "101101111",
   "011000001010" when "101110000",
   "011000001101" when "101110001",
   "011000010000" when "101110010",
   "011000010011" when "101110011",
   "011000010110" when "101110100",
   "011000011001" when "101110101",
   "011000011100" when "101110110",
   "011000011111" when "101110111",
   "011000100010" when "101111000",
   "011000100101" when "101111001",
   "011000101000" when "101111010",
   "011000101011" when "101111011",
   "011000101111" when "101111100",
   "011000110010" when "101111101",
   "011000110101" when "101111110",
   "011000111000" when "101111111",
   "011000111011" when "110000000",
   "011000111110" when "110000001",
   "011001000001" when "110000010",
   "011001000100" when "110000011",
   "011001000111" when "110000100",
   "011001001011" when "110000101",
   "011001001110" when "110000110",
   "011001010001" when "110000111",
   "011001010100" when "110001000",
   "011001010111" when "110001001",
   "011001011010" when "110001010",
   "011001011110" when "110001011",
   "011001100001" when "110001100",
   "011001100100" when "110001101",
   "011001100111" when "110001110",
   "011001101010" when "110001111",
   "011001101110" when "110010000",
   "011001110001" when "110010001",
   "011001110100" when "110010010",
   "011001110111" when "110010011",
   "011001111011" when "110010100",
   "011001111110" when "110010101",
   "011010000001" when "110010110",
   "011010000100" when "110010111",
   "011010001000" when "110011000",
   "011010001011" when "110011001",
   "011010001110" when "110011010",
   "011010010001" when "110011011",
   "011010010101" when "110011100",
   "011010011000" when "110011101",
   "011010011011" when "110011110",
   "011010011111" when "110011111",
   "011010100010" when "110100000",
   "011010100101" when "110100001",
   "011010101000" when "110100010",
   "011010101100" when "110100011",
   "011010101111" when "110100100",
   "011010110011" when "110100101",
   "011010110110" when "110100110",
   "011010111001" when "110100111",
   "011010111101" when "110101000",
   "011011000000" when "110101001",
   "011011000011" when "110101010",
   "011011000111" when "110101011",
   "011011001010" when "110101100",
   "011011001110" when "110101101",
   "011011010001" when "110101110",
   "011011010100" when "110101111",
   "011011011000" when "110110000",
   "011011011011" when "110110001",
   "011011011111" when "110110010",
   "011011100010" when "110110011",
   "011011100101" when "110110100",
   "011011101001" when "110110101",
   "011011101100" when "110110110",
   "011011110000" when "110110111",
   "011011110011" when "110111000",
   "011011110111" when "110111001",
   "011011111010" when "110111010",
   "011011111110" when "110111011",
   "011100000001" when "110111100",
   "011100000101" when "110111101",
   "011100001000" when "110111110",
   "011100001100" when "110111111",
   "011100001111" when "111000000",
   "011100010011" when "111000001",
   "011100010110" when "111000010",
   "011100011010" when "111000011",
   "011100011110" when "111000100",
   "011100100001" when "111000101",
   "011100100101" when "111000110",
   "011100101000" when "111000111",
   "011100101100" when "111001000",
   "011100101111" when "111001001",
   "011100110011" when "111001010",
   "011100110111" when "111001011",
   "011100111010" when "111001100",
   "011100111110" when "111001101",
   "011101000001" when "111001110",
   "011101000101" when "111001111",
   "011101001001" when "111010000",
   "011101001100" when "111010001",
   "011101010000" when "111010010",
   "011101010100" when "111010011",
   "011101010111" when "111010100",
   "011101011011" when "111010101",
   "011101011111" when "111010110",
   "011101100010" when "111010111",
   "011101100110" when "111011000",
   "011101101010" when "111011001",
   "011101101110" when "111011010",
   "011101110001" when "111011011",
   "011101110101" when "111011100",
   "011101111001" when "111011101",
   "011101111100" when "111011110",
   "011110000000" when "111011111",
   "011110000100" when "111100000",
   "011110001000" when "111100001",
   "011110001011" when "111100010",
   "011110001111" when "111100011",
   "011110010011" when "111100100",
   "011110010111" when "111100101",
   "011110011011" when "111100110",
   "011110011110" when "111100111",
   "011110100010" when "111101000",
   "011110100110" when "111101001",
   "011110101010" when "111101010",
   "011110101110" when "111101011",
   "011110110010" when "111101100",
   "011110110101" when "111101101",
   "011110111001" when "111101110",
   "011110111101" when "111101111",
   "011111000001" when "111110000",
   "011111000101" when "111110001",
   "011111001001" when "111110010",
   "011111001101" when "111110011",
   "011111010001" when "111110100",
   "011111010100" when "111110101",
   "011111011000" when "111110110",
   "011111011100" when "111110111",
   "011111100000" when "111111000",
   "011111100100" when "111111001",
   "011111101000" when "111111010",
   "011111101100" when "111111011",
   "011111110000" when "111111100",
   "011111110100" when "111111101",
   "011111111000" when "111111110",
   "011111111100" when "111111111",
   "------------" when others;
    Y <= TableOut;
end architecture;

--------------------------------------------------------------------------------
--                           IntAdder_17_f400_uid72
--                     (IntAdderClassical_17_F400_uid74)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved 
-- Authors: Bogdan Pasca, Florent de Dinechin (2008-2010)
--------------------------------------------------------------------------------
-- Pipeline depth: 0 cycles

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;

entity IntAdder_17_f400_uid72 is
   port ( clk, rst, ce : in std_logic;
          X : in  std_logic_vector(16 downto 0);
          Y : in  std_logic_vector(16 downto 0);
          Cin : in  std_logic;
          R : out  std_logic_vector(16 downto 0)   );
end entity;

architecture arch of IntAdder_17_f400_uid72 is
begin
   process(clk)
      begin
         if clk'event and clk = '1' then
            if ce = '1' then
            end if;
         end if;
      end process;
   --Classical
    R <= X + Y + Cin;
end architecture;

--------------------------------------------------------------------------------
--                                 FPExp_BF16
--                           (FPExp_8_7_F400_uid2)
-- This operator is part of the Infinite Virtual Library FloPoCoLib
-- All rights reserved 
-- Authors: F. de Dinechin, Bogdan Pasca (2008-2013)
--------------------------------------------------------------------------------
-- Pipeline depth: 4 cycles

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
library std;
use std.textio.all;
library work;

entity FPExp_BF16 is
   port ( clk, rst, ce : in std_logic;
          X : in  std_logic_vector(8+7+2 downto 0);
          R : out  std_logic_vector(8+7+2 downto 0)   );
end entity;

architecture arch of FPExp_BF16 is
   component LeftShifter_8_by_max_16_F400_uid4 is
      port ( clk, rst, ce : in std_logic;
             X : in  std_logic_vector(7 downto 0);
             S : in  std_logic_vector(4 downto 0);
             R : out  std_logic_vector(23 downto 0)   );
   end component;

   component FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8 is
      port ( clk, rst, ce : in std_logic;
             X : in  std_logic_vector(9 downto 0);
             R : out  std_logic_vector(7 downto 0)   );
   end component;

   component FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34 is
      port ( clk, rst, ce : in std_logic;
             X : in  std_logic_vector(7 downto 0);
             R : out  std_logic_vector(16 downto 0)   );
   end component;

   component IntAdder_9_f484_uid60 is
      port ( clk, rst, ce : in std_logic;
             X : in  std_logic_vector(8 downto 0);
             Y : in  std_logic_vector(8 downto 0);
             Cin : in  std_logic;
             R : out  std_logic_vector(8 downto 0)   );
   end component;

   component ExpYTable_9_12_F400_uid68 is
      port ( clk, rst, ce : in std_logic;
             X : in  std_logic_vector(8 downto 0);
             Y : out  std_logic_vector(11 downto 0)   );
   end component;

   component IntAdder_17_f400_uid72 is
      port ( clk, rst, ce : in std_logic;
             X : in  std_logic_vector(16 downto 0);
             Y : in  std_logic_vector(16 downto 0);
             Cin : in  std_logic;
             R : out  std_logic_vector(16 downto 0)   );
   end component;

signal Xexn, Xexn_d1, Xexn_d2, Xexn_d3, Xexn_d4 :  std_logic_vector(1 downto 0);
signal XSign, XSign_d1, XSign_d2, XSign_d3, XSign_d4 :  std_logic;
signal XexpField :  std_logic_vector(7 downto 0);
signal Xfrac :  std_logic_vector(6 downto 0);
signal e0 :  std_logic_vector(9 downto 0);
signal shiftVal, shiftVal_d1 :  std_logic_vector(9 downto 0);
signal resultWillBeOne, resultWillBeOne_d1 :  std_logic;
signal mXu :  std_logic_vector(7 downto 0);
signal oufl0, oufl0_d1, oufl0_d2, oufl0_d3 :  std_logic;
signal shiftValIn :  std_logic_vector(4 downto 0);
signal fixX0 :  std_logic_vector(23 downto 0);
signal fixX, fixX_d1 :  std_logic_vector(16 downto 0);
signal xMulIn :  std_logic_vector(9 downto 0);
signal absK, absK_d1 :  std_logic_vector(7 downto 0);
signal minusAbsK :  std_logic_vector(8 downto 0);
signal K, K_d1 :  std_logic_vector(8 downto 0);
signal absKLog2, absKLog2_d1 :  std_logic_vector(16 downto 0);
signal subOp1 :  std_logic_vector(8 downto 0);
signal subOp2 :  std_logic_vector(8 downto 0);
signal Y :  std_logic_vector(8 downto 0);
signal expY, expY_d1 :  std_logic_vector(11 downto 0);
signal needNoNorm, needNoNorm_d1 :  std_logic;
signal preRoundBiasSig :  std_logic_vector(16 downto 0);
signal roundBit :  std_logic;
signal roundNormAddend :  std_logic_vector(16 downto 0);
signal roundedExpSigRes :  std_logic_vector(16 downto 0);
signal roundedExpSig, roundedExpSig_d1 :  std_logic_vector(16 downto 0);
signal ofl1 :  std_logic;
signal ofl2 :  std_logic;
signal ofl3 :  std_logic;
signal ofl :  std_logic;
signal ufl1 :  std_logic;
signal ufl2 :  std_logic;
signal ufl3 :  std_logic;
signal ufl :  std_logic;
signal Rexn :  std_logic_vector(1 downto 0);
constant g: positive := 2;
constant wE: positive := 8;
constant wF: positive := 7;
constant wFIn: positive := 7;
begin
   process(clk)
      begin
         if clk'event and clk = '1' then
            if ce = '1' then
               Xexn_d1 <=  Xexn;
               Xexn_d2 <=  Xexn_d1;
               Xexn_d3 <=  Xexn_d2;
               Xexn_d4 <=  Xexn_d3;
               XSign_d1 <=  XSign;
               XSign_d2 <=  XSign_d1;
               XSign_d3 <=  XSign_d2;
               XSign_d4 <=  XSign_d3;
               shiftVal_d1 <=  shiftVal;
               resultWillBeOne_d1 <=  resultWillBeOne;
               oufl0_d1 <=  oufl0;
               oufl0_d2 <=  oufl0_d1;
               oufl0_d3 <=  oufl0_d2;
               fixX_d1 <=  fixX;
               absK_d1 <=  absK;
               K_d1 <=  K;
               absKLog2_d1 <=  absKLog2;
               expY_d1 <=  expY;
               needNoNorm_d1 <=  needNoNorm;
               roundedExpSig_d1 <=  roundedExpSig;
            end if;
         end if;
      end process;
   Xexn <= X(wE+wFIn+2 downto wE+wFIn+1);
   XSign <= X(wE+wFIn);
   XexpField <= X(wE+wFIn-1 downto wFIn);
   Xfrac <= X(wFIn-1 downto 0);
   e0 <= conv_std_logic_vector(118, wE+2);  -- bias - (wF+g)
   shiftVal <= ("00" & XexpField) - e0; -- for a left shift
   -- underflow when input is shifted to zero (shiftval<0), in which case exp = 1
   resultWillBeOne <= shiftVal(wE+1);
   --  mantissa with implicit bit
   mXu <= "1" & Xfrac;
   -- Partial overflow/underflow detection
   ----------------Synchro barrier, entering cycle 1----------------
   oufl0 <= not shiftVal_d1(wE+1) when shiftVal_d1(wE downto 0) >= conv_std_logic_vector(16, wE+1) else '0';
   ---------------- cycle 0----------------
   shiftValIn <= shiftVal(4 downto 0);
   mantissa_shift: LeftShifter_8_by_max_16_F400_uid4  -- pipelineDepth=1 maxInDelay=2.2932e-09
      port map ( clk  => clk,
                 rst  => rst,
                 ce => ce,
                 R => fixX0,
                 S => shiftValIn,
                 X => mXu);
   ----------------Synchro barrier, entering cycle 1----------------
   fixX <=  fixX0(23 downto 7)when resultWillBeOne_d1='0' else "00000000000000000";
   xMulIn <=  fixX(15 downto 6); -- truncation, error 2^-3
   mulInvLog2: FixRealKCM_6_M3_0_1_log_2_unsigned_F400_uid8  -- pipelineDepth=0 maxInDelay=0
      port map ( clk  => clk,
                 rst  => rst,
                 ce => ce,
                 R => absK,
                 X => xMulIn);
   ----------------Synchro barrier, entering cycle 2----------------
   minusAbsK <= (8 downto 0 => '0') - ('0' & absK_d1);
   K <= minusAbsK when  XSign_d2='1'   else ('0' & absK_d1);
   ---------------- cycle 1----------------
   mulLog2: FixRealKCM_7_0_M9_log_2_unsigned_F400_uid34  -- pipelineDepth=0 maxInDelay=0
      port map ( clk  => clk,
                 rst  => rst,
                 ce => ce,
                 R => absKLog2,
                 X => absK);
   ----------------Synchro barrier, entering cycle 2----------------
   subOp1 <= fixX_d1(8 downto 0) when XSign_d2='0' else not (fixX_d1(8 downto 0));
   subOp2 <= absKLog2_d1(8 downto 0) when XSign_d2='1' else not (absKLog2_d1(8 downto 0));
   theYAdder: IntAdder_9_f484_uid60  -- pipelineDepth=0 maxInDelay=4.4472e-10
      port map ( clk  => clk,
                 rst  => rst,
                 ce => ce,
                 Cin => '1',
                 R => Y,
                 X => subOp1,
                 Y => subOp2);

   -- Now compute the exp of this fixed-point value
   table: ExpYTable_9_12_F400_uid68  -- pipelineDepth=0 maxInDelay=0
      port map ( clk  => clk,
                 rst  => rst,
                 ce => ce,
                 X => Y,
                 Y => expY);
-- signal delay at BRAM output = 1.75e-09
   needNoNorm <= expY(11);
   ----------------Synchro barrier, entering cycle 3----------------
   -- Rounding: all this should consume one row of LUTs
   preRoundBiasSig <= conv_std_logic_vector(127, wE+2)  & expY_d1(10 downto 4) when needNoNorm_d1 = '1'
      else conv_std_logic_vector(126, wE+2)  & expY_d1(9 downto 3) ;
   roundBit <= expY_d1(3)  when needNoNorm_d1 = '1'    else expY_d1(2) ;
   roundNormAddend <= K_d1(8) & K_d1 & (6 downto 1 => '0') & roundBit;
   roundedExpSigOperandAdder: IntAdder_17_f400_uid72  -- pipelineDepth=0 maxInDelay=4.4472e-10
      port map ( clk  => clk,
                 rst  => rst,
                 ce => ce,
                 Cin => '0',
                 R => roundedExpSigRes,
                 X => preRoundBiasSig,
                 Y => roundNormAddend);

   -- delay at adder output is 1.059e-09
   roundedExpSig <= roundedExpSigRes when Xexn_d3="01" else  "000" & (wE-2 downto 0 => '1') & (wF-1 downto 0 => '0');
   ----------------Synchro barrier, entering cycle 4----------------
   ofl1 <= not XSign_d4 and oufl0_d3 and (not Xexn_d4(1) and Xexn_d4(0)); -- input positive, normal,  very large
   ofl2 <= not XSign_d4 and (roundedExpSig_d1(wE+wF) and not roundedExpSig_d1(wE+wF+1)) and (not Xexn_d4(1) and Xexn_d4(0)); -- input positive, normal, overflowed
   ofl3 <= not XSign_d4 and Xexn_d4(1) and not Xexn_d4(0);  -- input was -infty
   ofl <= ofl1 or ofl2 or ofl3;
   ufl1 <= (roundedExpSig_d1(wE+wF) and roundedExpSig_d1(wE+wF+1))  and (not Xexn_d4(1) and Xexn_d4(0)); -- input normal
   ufl2 <= XSign_d4 and Xexn_d4(1) and not Xexn_d4(0);  -- input was -infty
   ufl3 <= XSign_d4 and oufl0_d3  and (not Xexn_d4(1) and Xexn_d4(0)); -- input negative, normal,  very large
   ufl <= ufl1 or ufl2 or ufl3;
   Rexn <= "11" when Xexn_d4 = "11"
      else "10" when ofl='1'
      else "00" when ufl='1'
      else "01";
   R <= Rexn & '0' & roundedExpSig_d1(14 downto 0);
end architecture;

